library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity ffdcN is
generic (N : integer := 2);
port( CLK : in  std_logic;
      RST : in  std_logic;
      EN  : in  std_logic;
      D   : in  std_logic_vector (N-1 downto 0);
      Q 	 : out std_logic_vector (N-1 downto 0)
);
end ffdcN;

architecture structural of ffdcN is
component ffdc is
port( CLK : in  std_logic;
	   RST : in  std_logic;
	   EN  : in  std_logic;
	   D   : in  std_logic;
	   Q   : out std_logic
);
end component;

begin

	gen_top: for i in 0 to N-1 generate
		ff_array: ffdc port
		map ( CLK => CLK,
				RST => RST,
				EN  => EN,
				D	 => D(i),
				Q	 => Q(i)
		);
	end generate;
	
end structural;
